setup violation problem

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I'm not an expert but I have some ideas (in no order of significance):

1. Use clock enables instead of counter clocks (preferably in a process to avoid gated clocks)

2. You could try using a pll to generate the lower clock

3. I think you can assign the counter signal as an global signal to help the router do it's job

Best Regards,

Ola Bångdahl

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Thank you for your suggestions, I will look into my code and try to optimize my design.