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Honored Contributor
Honored Contributorsetup violation problem
Hello, I have a problem related to timing setup violation, my device is EP2C20F484C7, and I use classic timing analyzer as timing analysis tool. In addition, I use one global clock running at...
Altera_ForumHonored Contributor
Honored ContributorDid you try to run the code onto your FPGA as well? Most probably the timing analyzer doesn't know (because you did not tell him) that he is crossing two different clock domains so the skew is only apparent. If this is true, you will see your FPGA working correctly. Try and let us know.
