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Honored Contributor
Honored Contributorsetup violation problem
Hello, I have a problem related to timing setup violation, my device is EP2C20F484C7, and I use classic timing analyzer as timing analysis tool. In addition, I use one global clock running at...
Altera_ForumHonored Contributor
Honored ContributorI'm not an expert but I have some ideas (in no order of significance):
1. Use clock enables instead of counter clocks (preferably in a process to avoid gated clocks) 2. You could try using a pll to generate the lower clock 3. I think you can assign the counter signal as an global signal to help the router do it's job Best Regards, Ola Bångdahl
