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Honored Contributor
Honored Contributorsetup violation problem
Hello, I have a problem related to timing setup violation, my device is EP2C20F484C7, and I use classic timing analyzer as timing analysis tool. In addition, I use one global clock running at...
Altera_ForumHonored Contributor
Honored ContributorThank you for reply, very helpful. I use lpm_counter to generate some signals as clocks. I don't know whether it is the reason that causes the clock skew. If it is, how can I rectify and optimize my design? It seems that sometimes I should need to use internal combinational logic to generate some clocks, and I know it may cause clock skew, how can I fix it?
