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Honored Contributor
Honored ContributorSet-up and hold time of ALTDDIO megafunction module
I am using the ALTDDIO megafunction in an Arria V device to capture incoming data of the order of 1Gbps and my timing simulation (using Time Quest Analyser) tells me that delays should be so adjusted...
Altera_ForumHonored Contributor
Honored ContributorSetup and hold requirements are essentially the same for all core registers, not only DDIO. I don't see a particular core register timing specification with the Arria V handbooks I checked (there may be newer revisions). But the requirement is reflected in the sample window specification for LVDS IO and discussed in the respective handbook parts.
