Serial Configuration Devices (EPCS16) question / Fast Read

I have a question about one of the operations being used in AS Configuration.

My FPGA is Cyclone-III, and my AS Configuration device is EPCS16.

I can see (using the scope) that upon AS Configuration, the Cyclone III first issues a read status opcode, then a read silicon id, and finally a fast read.

My question is (after looking at the Vol 2, Ch 3 Configuration Handbook section e.g. page 3-21), how does the FPGA know when to drive ncs back to a High level (at the end of the operation) ?

Does it have some kind of logic, or a lookup table, so after the result of getting the Silicon ID, it decides how many DCLK pulses should be issued, in order to read all sectors within the capacity of an EPCS16 ?

Or else (I think this is less likely), it's monitoring the data pattern and after seeing a certain signature, it knows that it reached the end of the configuration data ?

I just want to understand how the duration (for deassertion of nCS) is decided by the master (FPGA) ... so that I can't be missing the very last bit, for example, if nCS gets deasserted one cycle or slightly too early (or too late). (I just don't know whether I could be seeing a CRC error ... I think in the documentation they mention "Frame Error".)

I wonder whether there's a single Frame CRC for the entire EPCS memory contents, or it has a Frame CRC in each sector ??

Thanks for your help; Larry.