Forum Discussion
Occasional ContributorSDF generation for Cyclone V on Quartus 19.1 Standard Edition
Hi,
Simulation using a post-fit timing netlist, testing functional and timing performance is supported only for the Arria® II GX/GZ,Cyclone® IV, MAX® II, MAX V, and Stratix® IV device families.
You may refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qps-tp-simulation.pdf , Table 2, Page 5.
Thanks.
Best regards,
KhaiY
Occasional ContributorHi KhaiY,
thank you very much for your answer. In the table I see that Gate-level timing simulation is not supported for the Cyclone-V.
Nevertheless, according to the table you mentioned, Gate-level functional simulation is supported for Cyclone-V.
Could you please verify that the post-fit netlist used for the Gate-level functional simulation is located in the ./simulation/modelsim folder under the name <design_name>.vo?
Thank you in advance for your response.
Kind regards,
anm
Regular ContributorHi Anm,
The Verilog Output File is placed in the /<project directory>/simulation/<EDA simulation tool> directory.
Thanks.
Best regards,
KhaiY
