Forum Discussion
Altera_Forum
Honored Contributor
9 years agoDont create an array of std_logic, you're just redifining the std_logic_vector type. Just create an array of std_logic_vector in a package, then import it into your entity:
package my_types_pkg is
type hexout_array_t is array(0 to 5) of std_logic_vector(6 downto 0);
end package;
....
use work.my_types_pkg.all;
entity hexscroll is
port (
hexout : hexout_array_t
);
end entity hexscroll;