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Altera_Forum
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17 years ago

Scaling core clock of 100MHz to 23MHz & 20MHz

Hello All, I am using Altera Stratix II for my project. I have generated a PLL in LVDs mode(for a deserialization factor of 10 and date rates is 1000Mbps). The two available clock sources ...
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Altera_Forum
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17 years ago

Your logic apparently drives out a square wave to rx_channel_data_align. This can't work, cause it leaves no time for the updated result to propagate to rx_out, as I mentioned previously. I'm allowing a new data_align pulse after 8 clocks, as you can see from my example code. To evaluate DPA operation, it may be meaningful to apply a single pulse only and observe the results in simulator or SignalTap.