Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Scaling core clock of 100MHz to 23MHz & 20MHz

Hello All, I am using Altera Stratix II for my project. I have generated a PLL in LVDs mode(for a deserialization factor of 10 and date rates is 1000Mbps). The two available clock sources ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I tried with following code to align the word but its not working. I have taken "ready" signal to increment the address of the ram. Could you suggest any modifications?

Data_align : process (iRxClk,inUserReset)

-- variable count: integer:=1;

begin

if(inUserReset='0') then

rx_channel_data_align <= "0";

elsif(iRxClk'event and iRxClk='1') then

if (rx_channel_data_align = "1") then

rx_channel_data_align <= "0";

end if;

if(rx_dpa_locked="1") then

if (rx_out = "0100110101") then

rx_channel_data_align <= "0";

ready<='1';

else

rx_channel_data_align <= "1";

end if;

end if;

end if;

end process Data_align;