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Altera_Forum
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18 years ago

Scaling core clock of 100MHz to 23MHz & 20MHz

Hello All, I am using Altera Stratix II for my project. I have generated a PLL in LVDs mode(for a deserialization factor of 10 and date rates is 1000Mbps). The two available clock sources ...
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Altera_Forum
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18 years ago

Hiii!!1

The problem I have is clearly mentioned in page 17–12 and 17 -13 for the Stratix GX (please find below) document..... Thku very much... The only solution is to use a State Machine as mentioned by u in ur previous reply. Thku once again. So nice of u.

http://www.altera.com/literature/hb/sgx/sgx_sgx52013.pdf

lg,

Sa