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Altera_Forum
Honored Contributor
Honored ContributorScaling core clock of 100MHz to 23MHz & 20MHz
Hello All, I am using Altera Stratix II for my project. I have generated a PLL in LVDs mode(for a deserialization factor of 10 and date rates is 1000Mbps). The two available clock sources ...
Altera_ForumHonored Contributor
Honored ContributorDoes the DPA block behave the same in ModelSim, I mean i have introduced a transportation delay in my system and now i am trying to adjust DPA block and want to check how it actually behaves. I shall try to implement some statemachine concept as suggested by you. But, would it be possible for me to notice the chages in ModelSim before going on to the real hardware?
