Scaling core clock of 100MHz to 23MHz & 20MHz

Yes, the DPA control should use 100 MHz (or slower) in this case.

I just was aware, that my design is actually 4 modules x 8 LVDS channels x 4 bit deserialization factor. The train can be done separately for each of the 4 modules, DPA control within a train sequence is also separate for each LVDS channel. You should analyze the logic for one channel first, it's much more simple of course. The important thing is to assure, that the sender is actually transmitting the train pattern while DPA train is activated (for 256 clocks in my design).