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Altera_Forum
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17 years ago

Scaling core clock of 100MHz to 23MHz & 20MHz

Hello All, I am using Altera Stratix II for my project. I have generated a PLL in LVDs mode(for a deserialization factor of 10 and date rates is 1000Mbps). The two available clock sources ...
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Altera_Forum
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17 years ago

do u mean "rx_outclock port" u are using is the slow clk from External Pll or??? because I am using LVDS in External Pll mode. I dont have rx-outclock.