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Altera_Forum
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18 years ago

Scaling core clock of 100MHz to 23MHz & 20MHz

Hello All, I am using Altera Stratix II for my project. I have generated a PLL in LVDs mode(for a deserialization factor of 10 and date rates is 1000Mbps). The two available clock sources ...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Ohh is it. I am not using any statemachine, is this state machine also a part of Megacore or ?

I dint enable rx_outclock port, should i enable it in Megacore. If possible could u please send that state machine program to me?

Can i check this in ModelSim too. I mean the behaviour of DPA block.

Reg

sa