Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorScaling core clock of 100MHz to 23MHz & 20MHz
Hello All, I am using Altera Stratix II for my project. I have generated a PLL in LVDs mode(for a deserialization factor of 10 and date rates is 1000Mbps). The two available clock sources ...
Altera_ForumHonored Contributor
Honored ContributorYes, the "rollover point" or rx_cda_max constant apparently doesn't affect the initial cda position. The position is advanced by pulsing rx_channel_data_align. I'm using a state machine clocked with DESER slow clock (rx_outclock) to operate the cda logic, so i get pulses one rx_outclock in width. After a applying a pulse, you have to wait for the delay change to propagate through DESER until the new phase is visible at the output.
