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Altera_Forum
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17 years ago

Scaling core clock of 100MHz to 23MHz & 20MHz

Hello All, I am using Altera Stratix II for my project. I have generated a PLL in LVDs mode(for a deserialization factor of 10 and date rates is 1000Mbps). The two available clock sources ...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hi,

The document is not clearly explaining how to use Data Realignment Circutry inorder to align the word boandry. There is no change if in the word boundary when i change the programmable bit rollover point(1 to 11 bit-times).

Do u know how to introduce a pulse to the "rx_channel_data_align" input port

reg

sa