Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorScaling core clock of 100MHz to 23MHz & 20MHz
Hello All, I am using Altera Stratix II for my project. I have generated a PLL in LVDs mode(for a deserialization factor of 10 and date rates is 1000Mbps). The two available clock sources ...
Altera_ForumHonored Contributor
Honored Contributorhi after a long time sry was busy with some other work :(
I have gone through that document. It is given that using "rx_channel_data_align" one can insert bit latency into the serial data. I have tried for different bit insertions in Megacore but there is no change in the word alignment. Do u have any idea how to use this "rx_channel_data_align" input port such that the word alignment is effected?
