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Altera_Forum
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18 years ago

Scaling core clock of 100MHz to 23MHz & 20MHz

Hello All, I am using Altera Stratix II for my project. I have generated a PLL in LVDs mode(for a deserialization factor of 10 and date rates is 1000Mbps). The two available clock sources ...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

If I rember right, I found all necessary information in the alt_lvds Megafunction user manual. Some reference designs are also available from Altera website, but I'm not sure if they include the DPA/CDA train logic.