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Altera_Forum
Honored Contributor
Honored ContributorScaling core clock of 100MHz to 23MHz & 20MHz
Hello All, I am using Altera Stratix II for my project. I have generated a PLL in LVDs mode(for a deserialization factor of 10 and date rates is 1000Mbps). The two available clock sources ...
Altera_ForumHonored Contributor
Honored ContributorThanku. Ya! I think i need some kind of training pattern. Do u have any documents (pdf or so) related to this issue i mean how to train a DPA.
