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Altera_Forum
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18 years ago

sampled signal on falling or risins edge?

Hello, I have a beginner question. With the code below The signal in_width_pulse_n is wide of one period (clk_speed) My question is on signal old1_width_pulse_n I must be sampled it ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

I can add that use the falling rising not make your margin safer, but force your design to go twice faster. It's as if you use a clock of double frequency and on a rising edge clock you generate the data and on the following one you acquire it.

I really suggest you to not change the sampling edge and let the compiler do its work.