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Altera_Forum
Honored Contributor
Honored Contributor"Safe" state machine
Hi, Attached herewith is the Altera safe_state example. I want to build my code around this kind of state machine (for robust design). My question is why didn't you used "when others" in your ...
Altera_ForumHonored Contributor
Honored ContributorAn others case not representing existing states is meaningless, both in standard and safe encoded FSM. If I remember right, the empty others case has been required by previous VHDL versions.
one-hot will be the default encoding in most cases, thus it can be expected meaningless as well. The only drawback of safe enconding is a slight increase in LE usage, you can try yourself.
