USB is 3.3V not 5V TTL. It's also not LVDS as has been pointed out.
It's a bidirectional bus using two data lines which are sometimes bit not always in anti-phase (differential). On top of that the slave device needs to be able to signal to the host device using a specific pull-up/pull-down resistor values which cannot be emulated directly with the FPGA.
You also have to know exactly when to change the direction of the data bus - if you are driving onto the data lines and don't switch to tristate before the device at the other starts driving onto the data lines you will end up with bus contention which will not do anything any good.
The FPGA I/O pins are not designed for hosting USB interfaces. You would need a separate PHY.
USB is not designed to have devices placed in the middle of the bus unless they are specifically configured as USB Hubs. A hub is very different from a simple pass through. They are separate USB devices. The host talks to the hub directly, and asks it nicely to relay messages to other devices connected to the hub.