Honored Contributor
Honored ContributorWhat you are trying to do is not practical using a simple FPGA differential receiver / transmitter. Per USB docs:
--- Quote Start --- USB uses a differential transmission pair for data. This is encoded using NRZI and is bit stuffed to ensure adequate transitions in the data stream. On low and full speed devices, a differential ‘1’ is transmitted by pulling D+ over 2.8V with a 15K ohm resistor pulled to ground and D- under 0.3V with a 1.5K ohm resistor pulled to 3.6V. A differential ‘0’ on the other hand is a D- greater than 2.8V and a D+ less than 0.3V with the same appropriate pull down/up resistors. The receiver defines a differential ‘1’ as D+ 200mV greater than D- and a differential ‘0’ as D+ 200mV less than D-. The polarity of the signal is inverted depending on the speed of the bus. Therefore the terms ‘J’ and ‘K’ states are used in signifying the logic levels. In low speed a ‘J’ state is a differential 0. In high speed a ‘J’ state is a differential 1. usb transceivers will have both differential and single ended outputs. certain bus states are indicated by single ended signals on d+, d- or both. for example a single ended zero or se0 can be used to signify a device reset if held for more than 10ms. a se0 is generated by holding both d- and d+ low (< 0.3v). single ended and differential outputs are important to note if you are using a transceiver and fpga as your usb device. you cannot get away with sampling just the differential output. --- Quote End --- So your best bet is really to use a separate USB PHY device that understands the USB protocol at the hardware level.
