Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Ris/fall time?

Hello,

I am developing a simple test board for a cyclone FPGA (EP2C8T144). It is my very first FPGA project, and I want to build my own FPGA board.

Now, my question is:

Which rise and fall times can I expect on any I/O pin of the FPGA? I am not using LVDS. I just use simple 3.3V LVCMOS.

The problem is, that there will be reflections on longer tracks on the PCB, if the rise time is too short. How can I calculate the maximum allowed track length if I know the driver strength of the I/O pin (4 mA)?

Hope, somebody can help me! This would be very great.

Thanks a lot in advance and excuse my bad english (I am a student in Switzerland) :D

11 Replies

Show More
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    I suggest you to avoid connecting the FPGA output pins to input pins of the device that you are driving. Put a small series resistor (22ohm or 33ohm) in every track and you will avoid this kind of reflection problems independently of the track length.