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Honored Contributor
Honored ContributorRGMII Source Synchronous Timing Problem
Hi design: My design interfaces an RGMII Gigabit Ethernet running at 125 MHz with 4 bits of data and 1 bit for validity of data. Data & clock are edge-aligned at the PHY output ports: Da...
Altera_ForumHonored Contributor
Honored ContributorIs there a MAC in this design or are you just trying to capture the raw Phy data? I'm using the TSE MAC with RGMII interface to a Marvell Phy. But I do not use a PLL in the Rx clock path. The clock goes directly to the MAC. Your Rx path timing constraints look almost identical to mine with the exception of the PLL clocks.
