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Altera_Forum
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9 years ago

reset sync design logic

I have a question regarding reset sync logic . first of all what I understood about requirement of reset synchronization in design : - Reset will be asynchronous in nature. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Hello Kaz,

Thank you for very good explanation. Could you help me to understand following sentence more clearly?

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In type2 imagine reset violated register1,

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Could you elaborate this? Do you mean reset is released during 'setup' or 'hold' period of register 1 and hence it would take time much than Tco ( Tco - clock to output delay ) for register1 to provide stable output?

Regards,

Bhaumik