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Honored Contributor
Honored ContributorRemoving signaltap causes logic to work
Hi All, I am seeing something strange. I have a design with signaltap instantiated. It compiles without any timing errors. But it does not behave correctly in the hardware. Actually, there ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- go to Assignments -> Partitions Window. Set the partitions in your design(most likely it's just the default Top) to post-fit. This will lock down the placement and routing. --- Quote End --- If u add changes to the VHDL code, what will happen with the design if this is enabled?
