Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Removing signaltap causes logic to work

Hi All, I am seeing something strange. I have a design with signaltap instantiated. It compiles without any timing errors. But it does not behave correctly in the hardware. Actually, there ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

--- Quote Start ---

go to Assignments -> Partitions Window. Set the partitions in your design(most likely it's just the default Top) to post-fit. This will lock down the placement and routing.

--- Quote End ---

If u add changes to the VHDL code, what will happen with the design if this is enabled?