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Altera_Forum
Honored Contributor
15 years agoRemoving signaltap causes logic to work
Hi All, I am seeing something strange. I have a design with signaltap instantiated. It compiles without any timing errors. But it does not behave correctly in the hardware. Actually, there ...
Altera_Forum
Honored Contributor
15 years agoYeah! That is what confuses me. But I like your idea of preserving the partition and then moving the probe points.
Thx. Sanjay