Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

remote update reconfig fails at low temperatures

We have a design that we've been using for a couple of years now, but have just noticed an issue at low temperatures. The design uses a Stratix II EP2S30, an EPCS64 in fast AS mode, remote upda...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

The clock is provided by the FPGA. Other than selecting fast AS mode, I have no control over it. The compressed bitstream is just over 5e6 bits. At 188ms, that's a clock rate of 26.7MHz. This is consistent with the datasheet, which specifies a typical clock of 26MHZ for fast AS mode.