Hi, Is it customary and synthesizable to enter the initial value that different from 'zero' during reset state? for instance: " if reset = '1' then reg <= "01"; reg_1 <= x"11"; elsif(-----) then ~ end if; " reg - internal signal inside the code reg_1 - out put signal(FPGA envelop) Tnx

yes it is both customary as well as synthesisable. You will get warnings though about these registers powering up high, so be it. Implementation is based on inserting inverters at input/output of registers (termed funny as not gate pushback) However, the term of "fpga envelop" is not that customary, do yo mean fpga interface?

Thanks for your quick response. By "FPGA envelop" I meant I\O ports in design's High Entity. The one we assign pins in the Pin Planner (Quartus), regardless FPGA interface. For the conclusion, as I see I can use the preset inspite of warnings, am I wright? Tnx

Yes we all apply non-zeros at reset when necessary. So be assured and ignore those warnings from tool. The tool "knows" you want that at reset but because you might have unchecked "powerup Dontcare" setting, it then warns that it can't have those registers powerup low(and who cares?).

--- Quote Start --- Is it customary and synthesizable to enter the initial value that different from 'zero' during reset state? --- Quote End --- Yes, but only if -"-----" is an edge sensitive event, in other words you are inferring a register -you don't use more than one asynchronous set or reset for each register and don't want to assign a variable reset state (e.g. depending on an input)

--- Quote Start --- By "FPGA envelop" I meant I\O ports in design's High Entity. --- Quote End --- Yes, but be aware that assigning a default value other than '0' will prevent the fitter from placing the register in an IOB. In other words, if you make the default value '1' and use the FAST_OUTPUT_REGISTER assignment then the FAST_OUTPUT_REGISTER assignment will be ignored. This is because it physically gets implemented as an inverter before and after the register and there is no output inverter in an IOB. This behaviour may or may not be a problem depending on your timing requirements. Mark.

register's initial value during reset state

14 Replies

Altera_Forum
Honored Contributor
13 years ago
Okay. So I changed my code slightly and added an extra register between my logic and the output pin, set to reset high. That packs properly. So, I have these conditions:

Reset high, some slightly complex code for setting the state. Won't place in an IOE.
Same as (1) but only change is to reset low. Places in an IOE fine.
Same as (1) but with an additional register between the output of the state machine and the pin, set to reset high. Places in an IOE fine.

So it looks like the complexity of my logic is somehow tripping it up. NOT Gate Push-back doesn't seem to change the above behaviour.

Mark.
Altera_Forum
Honored Contributor
13 years ago
Just a thought. It could be that if a register is associated with too complex logic (bidirectional) e.g you drive it and read it back then the tool wouldn't pack it as io register.
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
Just a thought. It could be that if a register is associated with too complex logic (bidirectional) e.g you drive it and read it back then the tool wouldn't pack it as io register.
--- Quote End ---

Nope, it's a one way street and I never read it. If i look at the compiled floorplan of the version that doesn't pack it I can see no reason for it not packing. The output of the register goes straight to an output pin and nowhere else.

Mark.
Altera_Forum
Honored Contributor
13 years ago
Even if you read it back, Quartus is usually smart enough to duplicate the register: an LE instance to be read back and a IOE instance to drive the output.
Maybe you've hit some kind of corner case where Quartus fails to do the correct thing.

Forum Discussion

register's initial value during reset state

14 Replies

Recent Discussions

Part Status request

Agilex 7 DDR4 Reset and ADDR/CMD Clock PCB Implementation Documentation Discrepancy

Vcm for the clock input pins of agilex5 E-series FPGA A5ED065BB32AE5SR0

Arria 10: Remote Update Factory Fallback won't work & Watchdog does not trigger

IBIS models GTS banks agilex 5E