Honored ContributorHi,
Is it customary and synthesizable to enter the initial value that different from 'zero' during reset state? for instance: " if reset = '1' then reg <= "01"; reg_1 <= x"11"; elsif(-----) then ~ end if; " reg - internal signal inside the code reg_1 - out put signal(FPGA envelop) Tnx
Honored Contributoryes it is both customary as well as synthesisable.
You will get warnings though about these registers powering up high, so be it. Implementation is based on inserting inverters at input/output of registers (termed funny as not gate pushback) However, the term of "fpga envelop" is not that customary, do yo mean fpga interface?Honored ContributorThanks for your quick response.
By "FPGA envelop" I meant I\O ports in design's High Entity. The one we assign pins in the Pin Planner (Quartus), regardless FPGA interface. For the conclusion, as I see I can use the preset inspite of warnings, am I wright? TnxHonored ContributorYes we all apply non-zeros at reset when necessary. So be assured and ignore those warnings from tool. The tool "knows" you want that at reset but because you might have unchecked "powerup Dontcare" setting, it then warns that it can't have those registers powerup low(and who cares?).
Honored ContributorHonored ContributorHonored ContributorAt least on some devices (tried on a Cyclone III), the IOE registers can be configured to power up high.
Honored Contributorprocess (clock, reset)
begin
if (reset = '1') then
noe <= '1';
elsif rising_edge (clock) then
<some stuff>
end if;
end process;
According to the devive manuals, both Cylone III and Cyclone IV have the said feature:
--- Quote Start --- The IOE registers in each I/O block share the same source for the preset or clear features. You can program preset or clear for each individual IOE, but you cannot use both features simultaneously. You can also program the registers to power-up high or low after configuration is complete. If programmed to power-up low, an asynchronous clear can control the registers. If programmed to power-up high, an asynchronous preset can control the registers. This feature prevents the inadvertent activation of the active-low input of another device upon power-up. If one register in an IOE uses a preset or clear signal, all registers in the IOE must use that same signal if they require preset or clear. Additionally, a synchronous reset signal is available for the IOE registers. --- Quote End --- I didn't try however, if the feature is functional as claimed. For Cyclone V, asynchronous clear and preset functions of IOE registers aren't discussed in the device manual. But there's a "PRN" text in the registers.Honored ContributorI tested it with the following piece of code (and output delay constrains), and Quartus packed the output register in the IOE for Cyclone III, IV and V.
module q0 (
input logic reset,
input logic clk_i,
input logic x,
output logic y
);
logic r;
always_ff @ (posedge reset, posedge clk_i) begin
if (reset)
r <= 4'b1111;
else
r <= { r, x};
end
assign y = r;
endmoduleVery good! Thank you for spending the effort.
