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Altera_Forum
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9 years ago

Registering partition boundaries and reducing combinatorial logic

I have a module dac that is instantiated inside of module registers. The module instance dac drives pins dac_data_bus[11:0] at the top level. I am receiving TimeQuest recommendations to "register the partition boundaries for the path" and "reduce the levels of combinatorial logic."

As I understand it, reduction in the levels of combinatorial logic is to pipeline an operation.

Both dac and registers are driven by the same clock.

Is there a general design method that I can use to register partition boundaries and reduce combinatorial logic? What does this recommendation imply, and how do I fix it?

Here is the TimeQuest output:

Register the partition boundaries for the path from registers:registe...|dac_data_bus[0] (http://about<strong></strong>:blank#) to dac_data_bus[0] [hide details] (http://about<strong></strong>:blank#)

  • issue: cross-partition paths (rdb:cross-partition%20paths)

  • from: registers:registers|dac:dac|dac_data_bus
  • to: dac_data_bus
  • timequest analysis: }%20-to%20{dac_data_bus
  • partitions that should be merged:

  • hard_block:auto_generated_inst -> Top

&#9733;&#9733;&#9733;Reduce the levels of combinational logic for the path from registers:registe...|dac_data_bus[1] (http://about<strong></strong>:blank#) to dac_data_bus[1] [hide details] (http://about<strong></strong>:blank#)

  • issue: long combinational path (rdb:long%20combinational%20path)

  • from: registers:registers|dac:dac|dac_data_bus
  • to: dac_data_bus
  • timequest analysis: }%20-to%20{dac_data_bus
  • extra levels of combinational logic:

  • 2

&#9733;&#9733;&#9733;Reduce the levels of combinational logic for the path from registers:registe...|dac_data_bus[0] (http://about<strong></strong>:blank#) to dac_data_bus[0] [hide details] (http://about<strong></strong>:blank#)

  • issue: long combinational path (rdb:long%20combinational%20path)

  • from: registers:registers|dac:dac|dac_data_bus
  • to: dac_data_bus
  • timequest analysis: }%20-to%20{dac_data_bus
  • extra levels of combinational logic:

  • 2

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    It appears that this can be fixed by updating the SDC file to use multicycle constraints where a delay is added. I updated the SDC file and this seemed to work well.

    set_multicycle_path -from }] -to }] -setup 4
    set_multicycle_path -from }] -to }] -hold 1