Regarding PLL design

Hi,

Once a PLL has acquired the lock, it can maintain this locked condition within a range called the "hold-in range" that corresponds to the static stability limits of the loop. It is not recommended to make the PLL working in this range but rather in the normal operation range. This latter can be roughly determined if you know the loop bandwith Fn (see figure enclosed).

You can refer to the Stratix II device handbook (Section 1.Clock Management/Chapt.1 PLLs in Stratix II/§ Reconfigurable Bandwidth) to make you an idea of the PLL parameters. I guess implemented PLLs must be similar from Stratix II to other devices for preliminary.

I point out the formula given in the figure are only approximate but can provide you the order of magnitude for the minimum lock range you are loocking for. In my experience, I have been able to observe very (surprising !) lock range with Cyclone II PLL which can only be explained by some supposed "glue logic" or a "glue state machine" dedicated to the PLL block and that make the PLL VCO and programmable dividers lock the PLL over a very wide range !

Hope this will help.

Oliver