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Altera_Forum
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14 years ago

Reducing Rise Time of Max V

I have a Max V (570Z) which I've programmed as a large (100 bit) Paralell In Serial Out shift register. I communicate with the CPLD via SPI. When I shift the data out, I notice significant rin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Setting low current strength and possibly slow slew rate in pin options is another way to improve signal quality of I/Os that don't need highest speed.