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Altera_Forum's avatar
Altera_Forum
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13 years ago

Receiver to FPGA

Hi, My project goal is to connect a receiver of 15Mbps to computer through FPGA DE3/DE4. I want to ask which component should i connect my receiver? and if i need clk from the receiver as well? ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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At 15 Mbps you can also use a DPLL (running at 8x or 16x the bitrate) and get away with Cyclone devices (-6 speed grade perhaps for the x16 case)

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Right. With Cylone III and above, you can also implement a kind of soft CDR based on PLL dynamic phase shift capability, working at considerably higher data rates. I didn't mention Cyclone related solutions, because tzahi is explicitely asking for DE3/DE4 (Stratix based) dev kits.