Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorReceiver to FPGA
Hi, My project goal is to connect a receiver of 15Mbps to computer through FPGA DE3/DE4. I want to ask which component should i connect my receiver? and if i need clk from the receiver as well? ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I already have a comparator in my circuit (look at the image attached above) --- Quote End --- I have seen the image and noticed that the comparator isn't connected to the TIA output signal. Thus I don't recognize a relation to your question. --- Quote Start --- i can't use synchronous data stream because my circuit has no clock --- Quote End --- I don't agree. As said, Stratix can use soft CDR to extract the clock.
