Random results on FPGA

Yes.

Got it this time ;-)

I changed my clock constraint, I removed all gated clock definition because

using create_generated_clock or create_clock of those internal clock was cutting the timing analysis for those clocks that needs to be clocked balanced.

Adding them in hte same clock group was not helping.

I now just define the source clock node and quartus is able, by itself, to properly figure out the clock routing and properly balance the gated clocks.

I really think it is the end of story now ;-)