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Altera_Forum
Honored Contributor
13 years agoRandom results on FPGA
Hello, I'm using altera devices for about 10 years with quartus or quartus + synplify pro. I'm currently struggling for about a month !!! on this issue: Using the same netlist from synplify...
Altera_Forum
Honored Contributor
13 years ago --- Quote Start --- yeah, for some reason one clock that i define in a particular clock domains amongst otthers clock in the same domain, is breaking the timing path. Will look furter into that one Today. --- Quote End --- Anymore on your exciting progress.