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Altera_Forum
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13 years ago

Random results on FPGA

Hello, I'm using altera devices for about 10 years with quartus or quartus + synplify pro. I'm currently struggling for about a month !!! on this issue: Using the same netlist from synplify...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Yes, so it has to be always be careful with the SDC constraint, it is among the biggest challenge to debug when it gives random result. Well, great work to find out the root cause