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Altera_Forum
Honored Contributor
Honored ContributorRandom results on FPGA
Hello, I'm using altera devices for about 10 years with quartus or quartus + synplify pro. I'm currently struggling for about a month !!! on this issue: Using the same netlist from synplify...
Altera_ForumHonored Contributor
Honored ContributorI found it this time.
Problem was due to the internal clock definiton of the cpu clock domain. Doing that was cutting io, reset and other clock domains connection timing analysis. By removing those clock definition, I could see plainty of big timing violations (like 10 ns). Now it is stable. So when it was working it was by luck due to the place and route positioning.
