Random results on FPGA

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well, it looks like the hold time analysis is a bit weak in my project,

I added a overconstraint of 0.2 ns and that seems much better.

In the sdc:

foreach_in_collection all_clocks [get_clocks *] {

set_min_delay -from $all_clocks -to $all_clocks 0.2

}

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I found out that the problem was due to reset that was de-asserted internally on a wrong clock domain.