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Altera_Forum
Honored Contributor
Honored ContributorRandom results on FPGA
Hello, I'm using altera devices for about 10 years with quartus or quartus + synplify pro. I'm currently struggling for about a month !!! on this issue: Using the same netlist from synplify...
Altera_ForumHonored Contributor
Honored ContributorIt looks like I can created the un-stability by propagating a variable clock (programmable pll)in the design (which is not selected by software).
Could it be that a variation in frequency can lead to unstability in the FPGA (I get a warning about the output of the pll not being dedicated)?
