Random results on FPGA

It is working fine using 91 clocks and using those settings:

set_global_assignment -name FAMILY "Stratix III"

set_global_assignment -name DEVICE EP3SL340F1760C3

set_global_assignment -name TOP_LEVEL_ENTITY wlc_ip1302_gbb5_fpga_a

set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.1

set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:12:01 DECEMBER 11, 2012"

set_global_assignment -name LAST_QUARTUS_VERSION "12.1 SP1"

set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files

set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0

set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA

set_global_assignment -name DEVICE_FILTER_PIN_COUNT 1760

set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 3

set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256

set_global_assignment -name ENABLE_INIT_DONE_OUTPUT ON

set_global_assignment -name STRATIX_JTAG_USER_CODE 20130424

set_global_assignment -name USE_CONFIGURATION_DEVICE OFF

set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF

set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED WITH WEAK PULL-UP"

set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"

set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise

set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall

set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise

set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall

set_global_assignment -name FITTER_EFFORT "STANDARD FIT"

set_global_assignment -name FLOW_DISABLE_ASSEMBLER OFF

set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS OFF

set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE SPEED

set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON

set_global_assignment -name SMART_RECOMPILE ON

set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION ON

set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001

set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF

set_global_assignment -name NUM_PARALLEL_PROCESSORS 2

set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF

set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS OFF

set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"

set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON

set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF

set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON

set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1

set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1

set_instance_assignment -name SLEW_RATE 3 -to *

set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT"

set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF

set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF

set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF

set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON

set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM

set_global_assignment -name PRE_MAPPING_RESYNTHESIS OFF

set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL

set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP OFF

set_global_assignment -name MUX_RESTRUCTURE OFF

set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON

set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3

set_global_assignment -name AUTO_MERGE_PLLS OFF

set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS MAXIMUM

set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"

set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"

set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION AUTOMATICALLY

set_global_assignment -name SEED 2

set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT FAST

set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON

set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON

set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION AUTOMATICALLY

set_global_assignment -name ROUTER_REGISTER_DUPLICATION OFF

set_global_assignment -name ENABLE_DRC_SETTINGS OFF

set_global_assignment -name AUTO_GLOBAL_CLOCK ON

set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF

set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES OFF

set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES OFF

set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC OFF

set_global_assignment -name DSP_BLOCK_BALANCING OFF

set_global_assignment -name REMOVE_DUPLICATE_REGISTERS OFF

set_global_assignment -name AUTO_CARRY_CHAINS OFF

set_global_assignment -name AUTO_ROM_RECOGNITION OFF

set_global_assignment -name AUTO_RAM_RECOGNITION OFF

set_global_assignment -name AUTO_DSP_RECOGNITION ON

set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF

set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES OFF

set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION ON

set_global_assignment -name STRICT_RAM_RECOGNITION ON

set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF

set_global_assignment -name AUTO_RAM_BLOCK_BALANCING OFF

set_global_assignment -name BLOCK_DESIGN_NAMING QUARTUSII

set_global_assignment -name SYNTHESIS_EFFORT AUTO

set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL OFF

set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES OFF

set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION OFF

set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING OFF

set_global_assignment -name OPTIMIZE_FOR_METASTABILITY ON

set_global_assignment -name IGNORE_LCELL_BUFFERS ON

set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT ON

set_global_assignment -name SYNCHRONIZER_IDENTIFICATION OFF