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Altera_Forum
Honored Contributor
Honored ContributorRandom results on FPGA
Hello, I'm using altera devices for about 10 years with quartus or quartus + synplify pro. I'm currently struggling for about a month !!! on this issue: Using the same netlist from synplify...
Altera_ForumHonored Contributor
Honored ContributorWell, indeed, this is bad to use clock gating in FGPA.
The problem is that they use the clock gating feature to reduce the clock speed (so the duty cycle is far from 50%). Before I was removing the gating succh that all mappings were stable and consistent, but without the clock divison feature. Thanks for your feedback anyway.
