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Altera_Forum
Honored Contributor
Honored ContributorRandom results on FPGA
Hello, I'm using altera devices for about 10 years with quartus or quartus + synplify pro. I'm currently struggling for about a month !!! on this issue: Using the same netlist from synplify...
Altera_ForumHonored Contributor
Honored ContributorI think the report is too vague to seriously guess about the problem cause.
I'm surprised about the "lot of clock gating" point. By nature of the clock networks, FPGAs are not designed to implement clock gating effectively, with the exception of those cases where clock control blocks or PLL blocks hold in reset can be utilized. Timing analysis should still work, but we don't know much about the design, see my first point.
