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Altera_Forum
Honored Contributor
Honored Contributorram not working correctly
hi .. the fpga and vhdl master ... I want to ask about the ram ... I have a little problem in the call data that are saved on ram ... when I try to testbench or i simulate in single block o...
Altera_ForumHonored Contributor
Honored Contributorsory, was a little mistake...:D
when I add reset, the Data can come out correctly, but logic gate which used to be much .... and when reset I remove, ram can be realized but the Data come out incorrect ....
