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Altera_Forum
Honored Contributor
Honored ContributorRam instantiation problem in post transtlation
hi, my code instantiates 16 ROMS of 256 X 8 length each. but in post translate step, i observe in modelsim output that only 4 such ROMS are instantiated... wat may be the reason for such behav...
Altera_ForumHonored Contributor
Honored ContributorTo expand on FvM comment...
Is there an output from your design that depends on the read from all ROMs. If there is no logic output that depends on the read data from a ROM then the ROM will be deleted in synthesis. The ROMS may be read by a testbench but does the result affect an output pin?
