Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorQuestion on how Quartus II Synthesizes Circuit
Hi, I have a couple of questions related to the way Quartus 2 is performing the synthesis of simple verilog programs. I have notice that when I program simple verilog programs (just Boolea...
Altera_ForumHonored Contributor
Honored ContributorCan you post your Verilog? And what device are you targeting?
I find it a bit weird you're seeing LCELL in RTL viewer.. Anyway, The RTL viewer shows the high level interpretation the synthesis tools does of your code; it is not optimized. The tools then proceed to map what you see in the RTL viewer to FPGA resources, as efficiently as they can.
