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Altera_Forum's avatar
Altera_Forum
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13 years ago

Question on how Quartus II Synthesizes Circuit

Hi, I have a couple of questions related to the way Quartus 2 is performing the synthesis of simple verilog programs. I have notice that when I program simple verilog programs (just Boolea...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Can you post your Verilog? And what device are you targeting?

I find it a bit weird you're seeing LCELL in RTL viewer..

Anyway,

The RTL viewer shows the high level interpretation the synthesis tools does of your code; it is not optimized.

The tools then proceed to map what you see in the RTL viewer to FPGA resources, as efficiently as they can.