question of the FPGA state after different configuration process?

The question in doubt could be, if all initialisation action, that is carried out after power-on reset is also performed with an reconfiguaration? Particularily, if power-up level, that is low internally for all FPGA registers (but may be inverted by logic), is also restored with a reconfiguration. I think that this is the case, but I didn't found it exactly stated in device handbooks, also the term power-up level may give raise to doubts.